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U2786B
DECT PLL / TX IC
Description
The U2786B is an RF IC for low-power DECT transmit applications. The IC includes a complete PLL with 1-GHz prescaler, on-chip frequency doubler, biasing for off-chip VCO, an integrated TX filter and a modulationcompensation circuit for advanced closed-loop modulation concept. Electrostatic sensitive device. Observe precautions for handling.
Features
D 1-GHz PLL, frequency doubler, TX data filter (13.824-MHz/ 27.648-MHz reference clock) D Supply-voltage range: 2.7 V to 4.7 V D Low current consumption D Few external components D No mechanical tuning necessary D Switchable charge-pump current for enhanced switching time D 1 operational amplifier for active loop filter D Advanced closed-loop modulation (with 13.824-MHz/ 27.648-MHz reference clock) and open loop modulation supported
Block Diagram
PU TX_DATA 28 27 OLE 26 25 GND_D DAC 24 RF_IN VCO_BIAS n.c. GND_RF_IN 23 22 21 20 PU_MIN OP_OUT OP_P GND_OP 19 18 17 16 OP_N 15
Control logic
DAC
f :n
PC OP
+
-
MCC
PD
RC 3-wire bus 1 2 DATA CLOCK 3
f :n
FD 2f
f
GF CP
4 REF_CLK
5
6 I_CP_SW
7
8 FD_OUT1
9
10 VS
11
12 GND_CP
13
14 CP
ENABLE
LD
GND_FD_OUT
FD_OUT2
GF_DATA
VS_CP
14224
Figure 1. Block diagram
Ordering Information
Extended Type Number U2786B-MFS U2786B-MFSG3 Package SSO28 SSO28 Remarks Tube Taped and reeled
Rev.A1, 21-Dec-99
1 (17)
Preliminary Information
U2786B
Pin Description
CLOCK DATA ENABLE REF_CLK LD I_CP_SW 1 2 3 4 5 6 28 TX_DATA 27 PU 26 OLE 25 GND_D 24 DAC 23 RF_IN 22 GND_RF_IN
GND_FD_OUT 7 FD_OUT1 FD_OUT2
U2786B
8 9
21 VCO_BIAS 20 n.c. 19 PU_MIN 18 GND_OP 17 OP_OUT 16 15 OP_P OP_N
VS 10 GF_DATA 11
GND_CP 12 VS_CP 13 CP 14 Figure 2. Pinning
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VS
Pin 1
Symbol CLOCK
Function 3-wire bus: Clock input
Configuration
2
DATA
3-wire bus: Data input
1,2 and 3
Ref
3
ENABLE
3-wire bus: Enable input
5k (10k)
5k (10k)
2 (17)
Rev.A1, 21-Dec-99
Preliminary Information
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Pin 4 10 9 7 8 6 5 GND_FD_OUT Frequency-doubler buffer ground FD_OUT1 Frequency-doubler buffer output 1 Symbol REF_CLK FD_OUT2 I_CP_SW LD VS Supply voltage Frequency-doubler buffer output 2 Charge-pump current switch Lock detect output Function Reference frequency input
6 4 5k (10k) 10k 100 VS 5k (10k) VS VS
Rev.A1, 21-Dec-99 Configuration
VS 5 10k 8,9 7 Ref
Preliminary Information
U2786B
3 (17)
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U2786B
Pin 11 20 18 19 17 16 15 12 13 14 Symbol GF_DATA GND_OP PU_MIN GND_CP VS_CP CP OP_OUT OP_N OP_P n.c. Operational-amplifier ground 3-wire bus: Data-hold enable in powerdown mode Not connected
AB-Control
4 (17) Operational-amplifier output Operational-amplifier non-inverting input Operational-amplifier inverting input Charge-pump ground Charge-pump supply voltage Charge-pump output Function Modulation output (Gaussian filtered data signal)
15 VS VS VS 14
Preliminary Information
Configuration
12
Rev.A1, 21-Dec-99
13 17 11 18 16 18
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Pin 21 25 26 24 22 23 GND_RF_IN RF_IN Symbol VCO_BIAS GND_D OLE DAC Digital ground Open-loop enable input DAC for VCO pretune RF input ground RF input from VCO to doubler and PLL Function VCO bias voltage output
23 26 1.5k 10k 5k (10k) 1k VS
Rev.A1, 21-Dec-99 Configuration
VS VS 5k (10k) VS 1.5k 21 24 Ref 22
Preliminary Information
U2786B
5 (17)
AAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A
U2786B
Pin 27 28 TX_DATA Symbol PU Digital TX data input to Gaussian filter and modulation compensation circuit Function Power-up input (active high)
27 28 20k 10k 25k 5k (10k) 10k 25k 5k (10k) VS
CP FD OP MCC PD VCO
Functional Blocks
6 (17) Charge pump Frequency doubler Amplifier for loop filter Modulation-compensation circuit Phase detector Voltage-controlled oscillator RC DAC GF LF PC
Preliminary Information
DA converter for pretuning of VCO Gaussian filter for transmit data Loop filter Programmable counter = MC (main counter) + SC (swallow counter) Reference counter Configuration Rev.A1, 21-Dec-99
10k Ref 140k
U2786B
Absolute Maximum Ratings
All voltages are referred to GND (Pins 7, 12, 18, 22 and 25). Supply voltage Logic input voltage Junction temperature Storage temperature Parameters Pins 10 and 13 Pins 1, 2, 3, 6, 26, 27 and 28 Symbol VS VIN Tjmax Tstor Min. - 0.3 -40 Typ. Max. 5.0 5.0 150 150 Unit V V _C _C
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 130 Unit K/W
Operating Range
Supply voltage Ambient temperature Parameter Pins 10 and 13 Symbol VS Tamb Min. 2.7 -25 Typ. 3.0 +25 Max. 4.7 +85 Unit V _C
Electrical Characteristics
Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25_C. Parameters Power supply Standby current Supply current Test Conditions / Pins Symbol Min. Pin 10 VPU = low level = `0' IS,OFF RX (OLE = `1') IS TX (OLE = `0') IS TX, MCC on IS TX, MCC, GF on IS TX, MCC, GF, OP on IS TX, MCC, GF, OP, FD on IS Supply current CP VVS_CP = 3 V, PLL in lock ICP condition Pin 14 Frequency doubler fRF_IN = 900 MHz (Pin 23) Pins 8 and 9 (differential) Output power PRF_IN= -10 dBm PFD_OUT - 10 Zload = 50 (differential) Pins 8 and 9 Harmonic suppression 2nd + 3rd; PRF_IN= -10 dBm HS - 20 Pins 8 and 9 Subharmonic suppression PRF_IN= -10 dBm SHS - 20 Pins 8 and 9 Typ. 1 6 11.5 13.2 12.8 15 25.8 1 Max. 10 Unit A mA mA mA mA mA mA A
-5
-3
dBm
dBc dBc
Rev.A1, 21-Dec-99
7 (17)
Preliminary Information
U2786B
Electrical Characteristics (continued)
Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25_C. Parameters PLL Input frequency Input voltage Test Conditions / Pins Pin 23 fRF_IN = 800 to 1000 MHz AC-coupled sinewave, Pin 23 Symbol fRF_IN VRF_IN Min. 800 20 Typ. Max. 1000 200 Unit MHz mVRMS
Scaling factor prescaler SPSC 32/33 Scaling factor main counter SMC 31/32/33/34 Scaling factor swallow SSC 0 31 counter External reference input AC-coupled sinewave fREF_CLK 5 28 MHz frequency Pin4 External reference input AC-coupled sinewave VREF_CLK 50 250 mVRMS voltage Pin4 Scaling factor reference Pin4 SRC 12/16/24/32 counter Charge pump active when RX, TX Pin 14 Output current VI_CP_SW = `0' ICP_1 1 mA VCP =VVS_CP / 2 VI_CP_SW = `1' ICP_5 5 mA VCP = VVS_CP / 2 Current scaling factor See bus protocol D0...D2 CPCS 60 130 % ICP = CPCS x ICP_TYP Leakage current IL 100 pA Operational amplifier Power-gain bandwidth Pin 17 PGBW 10 MHz Excess phase Rload = 1 k, Cload = 15 pF 80 degree Pin 17 Input offset voltage Pins 15 and 16 Voffs 1 mV Open-loop gain Pin 17 g 70 dB Output voltage range Pin 17 Vout 0.3 VS - 0.3 V Common-mode input voltage Pins 15 and 16 Vin 0.3 VS - 0.3 V Modulation-compensation circuit @ max. DSV 64, MCC only for fREF_CLK = 13.824MHz or 27.648 MHz Oversampling fREF_CLK= 13.824 MHz or OVS 6 27.648 MHz Integration counter MAC - 511 511 Current scaling factor See bus protocol E3...E5 MCCS 60 130 % Gaussian transmit filter (Gaussian shape BxT = 0.5) fREF_CLK has to be chosen ! Tx data filter clock fREF_CLK = 13.824 MHz, TX, fTXFCLK 6.912 MHz 12 taps in filter fREF_CLK = 27.648 MHz, TX, fTXFCLK 6.912 MHz 12 taps in filter Maximum output current Polarity see bus protocol D13 |IGF_DATA| 8.5 A Pin 11 Current scaling factor See bus protocol D6...D8 GFCS 60 130 % IGF_DATA = GFCS x IGF_TYP Pin 11
8 (17)
Rev.A1, 21-Dec-99
Preliminary Information
U2786B
Electrical Characteristics (continued)
Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25_C. Parameters VCO biasing Bias voltage Test Conditions / Pins Pin 21 Standby, PU = `0' Symbol Min. Typ. Max. Unit
VVCO 1.5 V VVCO 0 10 mV Temperature coefficient TC - 3.3 mV/K DAC for VCO PRETUNE 3-bit programming, see BUS protocol D3....D5 Pin 24 DAC low level Iload = 1 A VDAC_min 0.3 V DAC step level Nonlinear (see D3...D5) VDAC_step V DAC high level Iload = 1 A VDAC_max 2.25 V Output impedance RDAC_out 10 k Lock-detect output Lock-detect output, locked = `1', unlocked = `0' LD test-mode output test modes see bus protocol E0....E2 Pin 5 Leakage current VOH = 4.5 V Pin5 IL 5 A Saturation voltage IOL = 0.5 mA Pin 5 VSL 0.4 V 3-wire bus Clock Pin 1 fclock 1.152 MHz Logic input levels (CLOCK, DATA, ENABLE, I_CP_SW, OLE, GF_DATA) Pins 1, 2, 3, 6, 26 and 28 High input level =`1' ViH 1.5 V Low input level =`0' ViL 0.5 V High input current =`1' IiH -5 5 A Low input current =`0' IiL -5 5 A Standby control Power up High input level PU = `1' Pin 27 VPU 2.0 V Low input level PU = `0' Pin 27 VPU,OFF 0.7 V DATA hold enable High input level PU_MIN = `1' Pin 19 VPU_MIN 2.0 V Low input level PU_MIN = `0' Pin 19 VPU_MIN 0.7 V Power up PU = `1' High input current VPU = 3 V IPU 100 125 150 A VPU = 4.5 V Pin 27 220 300 420 A Standby PU = `0', PU_MIN = `1' High input current VPU_MIN = 3 V Pin 19 IPU_MIN,ON 21 A Standby PU = `0' PU_MIN = `0' Low input current VPU = 0 V Pin 27 IPU,OFF 0.1 A VPU_MIN = 0.5 V Pin 19 IPU_MIN,OFF 1 A Settling time: VS = 0 Switched from tsoa < 10 s active operation VS = 0 to VS = 3 V Settling time: standby Switched from standby to tssa < 10 s active operation PU = `1' Settling time: active Switched from PU = `1' to tsas <2 s operation standby standby
Rev.A1, 21-Dec-99
9 (17)
Preliminary Information
U2786B
PLL Principle
RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD (SMC 32 + SSC) fVCO fPD CP VCO Frequency doubler FD fOUT
Phase frequency detector PD
FD_OUT DAC fPD = 864 kHz GF_DATA Modulation compensation MMC Gaussian filter GF
Controlled phase shifting
Reference counter RC REF_CLK 10.368MHz* 13.824MHz 20.736MHz* 27.648MHz** SRC 12 16 24 32
6.912MHz
* MCC and GF not possible **Reference counter not possible
1.152 Mbit/s
PLL reference Frequency REF_CLK Baseband controller
TX_DATA
Figure 3. PLL principle
10 (17)
Rev.A1, 21-Dec-99
Preliminary Information
U2786B
The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for an optional DECT band extension. Intermediate frequencies of 110.592 and 112.32 MHz are supported.
Table 1. LO frequencies
Mode TX
fIF/MHz
RX
110,592
112,32
Channel C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
fANT/MHz 1897,344 1895,616 1893,888 1892,16 1890,432 1888,704 1886,976 1885,248 1883,52 1881,792 1897,344 1895,616 1893,888 1892,16 1890,432 1888,704 1886,976 1885,248 1883,52 1881,792 1897,344 1895,616 1893,888 1892,16 1890,432 1888,704 1886,976 1885,248 1883,52 1881,792
fLO/MHz 948,672 947,808 946,944 946,08 945,216 944,352 943,488 942,624 941,76 940,896 893,376 892,512 891,648 890,784 889,92 889,056 888,192 887,328 886,464 885,6 892,512 891,648 890,784 889,92 889,056 888,192 887,328 886,464 885,6 884,736
2fLO/MHz 1897,344 1895,616 1893,888 1892,16 1890,432 1888,704 1886,976 1885,248 1883,52 1881,792 1786,752 1785,024 1783,296 1781,568 1779,84 1778,112 1776,384 1774,656 1772,928 1771,2 1785,024 1783,296 1781,568 1779,84 1778,112 1776,384 1774,656 1772,928 1771,2 1769,472
SMC 34 34 34 34 34 34 34 34 34 34 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
SSC 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 1 0
Table 2. Limits
Mode RX
RX
fIF/MHz TX 110,592 112,32 TX 110,592 112,32
fmin
fmax
fANT/MHz 1714,176 1824,768 1826,496 1933,632 2044,224 2045,952
fLO/MHz 857,088 857,088 857,088 966,816 966,816 966,816
2fLO/MHz 1714,176 1714,176 1714,176 1933,632 1933,632 1933,632
SMC 31 31 31 34 34 34
SSC 0 0 0 31 31 31
Formula fANT C1 - fANT C2 = 1,728MHz for TX fLO = fANT / 2 for RX fLO = (fANT - fIF) / 2
SMC = integer (fLO / 0,864 MHz / 32) SSC = MOD ((fLO / 0,864 MHz) / 32)
Rev.A1, 21-Dec-99
11 (17)
Preliminary Information
U2786B
Control Signals
I_CP_SW LD OLE DAC PU PU_MIN Input for switching charge-pump current by factor 5 Output, which is active after PLL is locked and testmode output (according to programmed testmode) Enable input for open-loop modulation DAC for VCO band switch Hardware power up / standby of complete PLL / TX - IC Data-hold enable of 3-wire bus in power-down mode Standard Settings 0
0 1 1
Serial Programming Bus
Reference and programmable counters can be programmed by the 3-wire bus (CLOCK, DATA and ENABLE). Beside this information additional control bits as phase detector polarity and scaling of charge-pump currents as well as internal currents for Gaussian lowpass filter and modulation compensation circuit can be transferred. After setting ENABLE signal to low condition, the data status is transferred bit by bit on the rising edge of the CLOCK signal into the shift register, starting with the MSB-bit. After ENABLE returning to high condition the programmed information is loaded into the addressed latches, according to the addressbit condition (last bit). Additional leading bits are ignored and there is no check made how many pulses have arrived during ENABLElow condition. The bus then returns to a low current standby mode until the ENABLE signal changes to low again. During standby of the PLL the information in the registers of the PLL is maintained. In powerdown mode of complete PLL/TX-IC (PU is set to 0) there are two possible states of the 3-wire bus. 1. PU_MIN = 1: the informations in the registers of 3-wire bus are maintained 2. PU_MIN = 0: the informations in the registers of 3-wire bus are lost
MSB
Data bits D22 RC 0 1 0 1 D21 D20 D19 D18 SC 1 1 1 0 D17 D16 D15 D14 MC 0 0 D13 D12 Phase 1 0 D11 D10 GF 1 D9 MCC 1 1 D8 D7 GFCS 0 0 1 D6 D5 D4 DAC 0 0 1 D3 D2 D1 CPCS 0 0 D0
LSB
Address bit A0 1 1
Data bits E7 FD E6 OP 1 1 E5 E4 MCCS 0 0 0 E3 E2 E1 TEST 0 0 E0
Address bit A0 0 0
Standard bit setting:
Word 1
Word 2
1
12 (17)
Rev.A1, 21-Dec-99
Preliminary Information
U2786B
PLL Settings
D22 0 0 1 1 RC (Reference Counter) D21 0 1 0 1 SRC 32 12 16 24 D15 0 0 1 1 MC (Main Counter) D14 0 1 0 1 SMC 31 32 33 34
D20 0 0 0 0 1 1 *
D19 0 0 0 0 1 1
SC (Swallow Counter) D18 D17 0 0 0 0 0 1 0 1 1 1 1 1
D16 0 1 0 1 0 1
SSC * 0 1 2 3 ... 30 31
SSC = [D16] x 20 + [D17] x 21 + ... [D20] x 24 SPGD = 32 x SMC + SSC
Phase Settings
D13 0 1 Phase of GFDATA GFDATA Source Sink
Current Saving Power up/down Settings
D10 0 1 GF (Gaussian Filter) OFF (RX) ON (TX)
Phase of MCC Internal Connection D12 MCC Data 0 Inverted 1 Normal
E7 0 1
FD (Frequency Doubler) OFF ON
D9 0 1
MCC (Modulation Compensation Circuit) OFF (RX or OLE = `1') ON (TX)
D11 0 1
Phase of CP (Charge Pump) fR > fP fR < fP f R = fP ISink ISource High imp ISource ISink High imp
E6 0 1
OP (OpAmp) OFF ON
Rev.A1, 21-Dec-99
13 (17)
Preliminary Information
U2786B
Current Gain Settings
GFCS (Gaussian Filtered Current Settings) D8 D7 D6 GFCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% MCCS (Modulation Compensation Settings) E5 E4 E3 MCCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130%
Pretune DAC Voltage Settings
CPCS (Charge-Pump Current Settings) D2 D1 D0 CPCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% D5 0 0 0 0 1 1 1 1 Pretune DAC Voltage D4 D3 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 DAC / V 0.33 0.43 0.60 0.79 1.02 1.38 1.73 2.24
Test Mode Settings
D11 x 0 1 x x 0 1 x E2 0 0 0 0 1 1 1 1 E1 0 0 1 1 0 0 1 1 Test Output Pin (Lock Detect) E0 Signal at Lock Detect and PLL Mode 0 Lock detect mode 1 RC out and CP active 0 PC out and CP active (phase changed) 1 MCCTEST (RC out divided by 2048 or 4096) 0 CP tristate only 1 RC out and CP high impedance 0 PC out and CP high impedance 1 GFTEST (RC out divided by 4 or 8) CP Mode Active Active Active Active High impedance High impedance High impedance High impedance
3-Wire Bus Protocol Pulse Diagram
MSB ENABLE DATA CLOCK LSB
Figure 4. Pulse diagram
14 (17)
Rev.A1, 21-Dec-99
Preliminary Information
U2786B
3-Wire Bus Protocol Timing Diagram
DATA CLOCK ENABLE TL TS TC TH TEC TED TT
Figure 5. Timing diagram
Description Set time DATA to CLOCK Hold time DATA to CLOCK CLOCK pulse width Set time ENABLE to CLOCK Hold time ENABLE to CLOCK Hold time ENABLE to DATA Time between two protocols
Symbol TS TH TC TL TEC TED TT
Min. Value 434 0 434 217 0 0 868
Unit ns ns ns ns ns ns ns
Typical Application Circuit
PU_MIN PU_MIN VCO OLE PU TX_DATA PRETUNE RFIN VCO_BIAS n.c. LOOP-FILTER LF
VS/2 OP_OUT OP_P OP_N
U2786B
CP CLOCK DATA ENABLE REF_CLK LD I_CP_SW MOD
VS FD_OUT1 FD_OUT2
VS_CP
14226
Figure 6. Application circuit
Rev.A1, 21-Dec-99
15 (17)
Preliminary Information
U2786B
Package Information
Package SSO28
Dimensions in mm
9.10 9.01 5.7 5.3 4.5 4.3
1.30 0.25 0.65 8.45 28 15 0.15 0.05 6.6 6.3 0.15
technical drawings according to DIN specifications
13018
1
14
16 (17)
Rev.A1, 21-Dec-99
Preliminary Information
U2786B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev.A1, 21-Dec-99
17 (17)
Preliminary Information

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